1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having Dual-STI (Shallow Trench Isolation) and a manufacturing method thereof.
2. Description of the Background Art
In order to achieve smaller size or high speed of a semiconductor element, a distance between isolation structures should be narrowed. As a conventional method of forming an element isolation area, LOCOS (local oxidation of silicon) has commonly been employed, however, LOCOS cannot sufficiently meet such demand for a smaller size. Accordingly, STI has recently been employed instead of LOCOS.
According to a conventional method of manufacturing an STI, initially, a silicon oxide film, polysilicon, and a silicon nitride film are stacked on a semiconductor substrate such as a silicon substrate. Thereafter, a resist having an opening for an element isolation area is formed by photolithography. Using this resist as a mask, the silicon oxide film, the polysilicon, the silicon nitride film, and the semiconductor substrate are anisotropically etched, so as to form a trench (groove). After the resist is removed, a silicon oxide film is deposited on an entire surface by using, for example, HDP (High density plasma)-CVD (Chemical Vapor Deposition). Extra silicon oxide film is removed by CMP (Chemical Mechanical Polishing) using the silicon nitride film as a stopper, and an STI having a trench embedded with the silicon oxide film is formed.
In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a withstand voltage in isolation is different between a memory cell area and a peripheral circuit area. Specifically, as an applied voltage is lower in the memory cell area than in the peripheral circuit area, the withstand voltage in isolation required in the STI in the memory cell area is low. Therefore, the depth of the STI in the memory cell area is made smaller than that in the peripheral circuit area, so that an area occupied by the memory cell area is decreased. In this manner, a structure in which a depth of the STI is different between areas is referred to as Dual-STI.
Conventionally, Dual-STI has normally been formed in the following manner. Initially, a shallow trench portion is formed in the memory cell area and the peripheral circuit area with the conventional method of manufacturing the STI. Thereafter, the memory cell area is covered with a resist. Using the resist and a silicon nitride film as a mask, the semiconductor substrate is anisotropically etched, so as to form a deep trench portion within the shallow trench portion in the peripheral circuit area. After the resist is removed, the silicon oxide film is deposited on the entire surface. Extra silicon oxide film is removed by CMP, using the silicon nitride film as a stopper, so as to form Dual-STI having the shallow trench portion and the deep trench portion embedded with the silicon oxide film. After the Dual-STI is formed, the silicon oxide film, polysilicon, and the silicon nitride film formed on the silicon substrate are removed.
Japanese Patent Laying-Open No. 05-121537 discloses a technique to form a shallow trench portion in a collector isolation area and to form a deep trench portion in an element isolation area. According to Japanese Patent Laying-Open No. 05-121537, a mask pattern having a width in the collector isolation area smaller than that in the element isolation area is formed, and the semiconductor substrate is etched utilizing a characteristic that etching progresses slowly in a narrow portion.
In addition, Japanese Patent Laying-Open No. 2001-044273 discloses a method of forming an STI using a TEOS (Tetra Ethyl Ortho Silicate) film. According to Japanese Patent Laying-Open No. 2001-044273, a pad oxide film, a silicon nitride film, and a TEOS film are stacked on the silicon substrate. Using a resist formed on the TEOS film as a mask, the pad oxide film, the silicon nitride film, and the TEOS film are etched. After the resist is removed, the silicon substrate is etched using the TEOS film as a mask, so as to form a trench.
Moreover, in Stephen N. Keeney, “A 130 nm Generation High Density Etox™ Flash Memory Technology,” page 11. [online]; <URL: ftp://download.intel.com/research/silicon/0.13micronflash_pres.pdf>, an example of a flash memory using Dual-STI is shown.
As described above, according to the conventional method of forming Dual-STI, the memory cell area is covered with the resist. Using the resist and the silicon nitride film as a mask, the semiconductor substrate is anisotropically etched, so as to form the deep trench portion in the peripheral circuit area. In forming the deep trench portion, the silicon nitride film formed in the memory cell area is covered with the resist. On the other hand, as the silicon nitride film formed in the peripheral circuit area serves as the mask during etching, it is not covered with the resist. Therefore, a part of the silicon nitride film formed in the peripheral circuit area is anisotropically etched, and a film thickness of the silicon nitride film in the peripheral circuit area becomes smaller than that in the memory cell area.
When the film thickness of the silicon nitride film in the peripheral circuit area becomes smaller than that in the memory cell area, reliability of a semiconductor device is lowered. Such a disadvantage will be described in the following.
When the film thickness of the silicon nitride film in the peripheral circuit area is smaller than that in the memory cell area, extra silicon oxide film remains particularly in a stepped portion at a boundary between the memory cell area and the peripheral circuit area in removing extra silicon oxide film on the silicon nitride film by using CMP. Thereafter, in removing the silicon nitride film or the like formed on the silicon substrate, remaining silicon oxide film serves as a mask, and the silicon nitride film or a polysilicon film under the silicon oxide film cannot be removed. Consequently, a defect such as generation of a foreign matter, short-circuiting, or defective shape is caused, resulting in lower reliability of a semiconductor device.
In addition, as an isolation height of the STI is defined by the silicon nitride film serving as a stopper film at the time of CMP, the isolation height of the STI in the peripheral circuit area becomes lower than that in the memory cell area. If the isolation height of the STI in the peripheral circuit area is lower than that in the memory cell area, films to be etched on the STI stepped portion will have different thicknesses when a conductive film serving as an electrode for forming an element such as a transistor is subsequently formed. Therefore, when this film is patterned, the conductive film may remain at the STI stepped portion or an underlying layer may be removed, which results in lower reliability of a semiconductor device.
According to the technique disclosed in Japanese Patent Laying-Open No. 05-121537, the depth is uniquely determined based on the width of the trench. Therefore, restriction in terms of layout is imposed on fabrication of the deep trench portion and the shallow trench portion. In addition, as this publication is silent about the isolation height, the problem as described above cannot be solved.
In addition, the technique disclosed in Japanese Patent Laying-Open No. 2001-044273 is not directed to manufacturing of Dual-STI in which a deep trench portion and a shallow trench portion having depths different from each other are formed. Therefore, this publication cannot solve the problem as described above.
Moreover, according to the technique disclosed in Stephen N. Keeney, “A 130 nm Generation High Density Etox™ Flash Memory Technology,” page 11. [online]; <URL: ftp://download.intel.com/research/silicon/0.13micronflash_pres.pdf>, the isolation structure height in the deep trench portion is smaller than that in the shallow trench portion. Therefore, the problem as described above cannot be solved. This publication discloses no means for solving the problem of extra silicon oxide film remaining in the stepped portion at the boundary between the memory cell area and the peripheral circuit area.